Field of the Invention
The present invention relates to a RF switches, and more particular to bulk RF switches fabricated using CMOS or BiCMOS fabrication techniques.
Related Art
RF Switches built from N-Type Field-Effect Transistors (NFETs) on bulk Silicon substrates using Complementary Metal-Oxide Semiconductor (CMOS) or BiCMOS processing techniques (herein referred to as “bulk CMOS RF switches) suffer from large parasitic capacitances due to the various P-N junctions that are inherent in conventional RF switches configurations. These parasitic capacitances manifest themselves in the form of lower RF impedance between the device and ground that leads to poor isolation (i.e., current leakage) of the switch in the off state (referred to as Coff).
FIGS. 8(A) and 8(B) are plan and cross-sectional side views showing a conventional NFET 50, which is representative of a typical conventional bulk CMOS RF switch. As indicated in FIG. 8(B), NFET 50 is formed on a base structure including a substrate 51 and an epitaxial layer 52. Epitaxial layer 52 is typically initially formed as a lightly N-doped epitaxial (N-epi) material on a p-type monocrystalline silicon substrate 51 using known techniques, and is then subjected to known doping processes such that the P-type or N-type dopants are diffused into corresponding regions of epitaxial 52 in order to change the electrical characteristics of these regions as described below.
As indicated in FIG. 8(A), NFET 50 includes functional structures fabricated in and over a volume of epitaxial layer 52 that is generally surrounded by field isolation 53, and located over an N-Type isolation implant (Deep N-Well) 54. For descriptive purposes, the volume of epitaxial layer 52 occupied by regions of NFET 50 include a first (lower) epi region 52-1, a second epi region 52-2 located over a first portion of first epi region 52-1, and a third portion 52-3 located over a second portion of first epi region 52-1. Field isolation 53 is typically formed using known shallow trench isolation techniques, but may include other isolation structure types. The various sections of field isolation 53 surrounding NFET 50 are also identified for descriptive purposes as end sections 53-1 and 53-2 (i.e., aligned in the X-axis direction), and side sections 53-3 and 53-4 (i.e., aligned in the X-axis direction). An intermediate field isolation section 53-5 is aligned parallel to end sections 53-1 and 53-2, and separates second epi region 52-2 from third epi region 52-3. Referring to FIG. 8(B), field isolation 53 extends into epitaxial layer 52 from an upper surface 52U, but does not extend entirely through epitaxial layer 52. Deep N-Well 54 is formed at the horizontal interface of epitaxial layer 52 and substrate 51 such that a first portion of the N-type dopant used to generate Deep N-well 54 occupies first epi region 52-1, and a second portion of the N-type dopant is diffused into an upper section of substrate 51.
NFET 50 generally includes functional structures formed in a P-Type NFET body implant (P-Well) 55, and also a N-Type body implant (N-Tap) element 56, and a P-type body implant (N-Tap) element 59. P-well 55 is formed by implanting a P-type dopant into second epi region 52-2 using a high-energy diffusion process such that P-Well 55 extends from an upper boundary 54U of Deep N-Well 54 to upper surface 52U of epitaxial layer 52, and from intermediate field isolation section 53-5 to end field isolation section 53-2. A polycrystalline silicon (polysilicon or poly) gate structure G is formed over P-well 55 using known techniques, and then a source region S and a drain region D are formed in corresponding portions of P-well 55 using shallow N-type implants that are separated by a channel region CH, and a base contact B is formed in another corresponding portion of P-well 55 using a shallow P-type implant. Other functional portions and features of NFET 50, some of which being illustrated in FIG. 8(B), are omitted from mention for brevity. N-Tap element 56 includes an N-type contact region C and an N-type dopant 57 disposed in third epi region 52-3. N-type dopant 57 implanted into third epi region 52-3 using a high-energy diffusion process such that N-type dopant 57 extends from an upper boundary 54U of Deep N-Well 54 to upper surface 52U of epitaxial layer 52. Contact region C is formed simultaneously with the source and drain regions using shallow N-type implants, and is at upper surface 52U between end field isolation section 53-1 and intermediate field isolation section 53-5. P-Tap element 59 is formed simultaneously with P-Well 55, and is located outside the periphery of field isolation 53 (e.g., to the left of end field isolation section 53-1 in FIG. 8(B)).
Base contact B, N-Tap element 56 and P-Tap element 59 receive bias voltages that enhance the performance of NFET 50 by way of isolating the functional structures during operation. N-Tap 56 serves to facilitate maintaining Deep N-Well 56 at a desired voltage level (potential) during operation by way of conducting an N-well bias voltage Vbias-DNW from highly N-doped (N+) N-Tap surface contact implant C to Deep N-Well 54. Intermediate field isolation section 53-5 is disposed above the vertical interface between N-Tap epi region 52-3 and P-Well 55 and serves to isolate N-Tap contact implant C from highly P-doped (P+) body contact implant B, which is also formed at upper epitaxial layer surface 52U and serves as a contact point for an applied body bias voltage Vbias-PW that maintains P-Well 55 at a desired voltage level during operation. Referring to the left side of FIG. 8(B), external P-doped implant (P-Tap) element 59 forms another “tap” region that connects substrate 51 to upper epitaxial layer surface 52U. Note that P-Tap element 59 is separated from N-Tap 56 by a retained (i.e., lightly N-doped) portion 52R of intrinsic N-epi material, which is located under end field isolation section 53-1 and therefore protected from doping during formation of N-Tap element 56 and P-Tap element 59. With the bias voltages applied as mentioned above, NFET 50 is switched into a closed (on) operating state (i.e., such that current flows from source implant S and drain implant D through channel region CH) by way of applying a sufficiently high gate voltage to gate structure G, and NFET 50 is switched into an open (off) operating state, in which no current flows in channel region CH, by way of applying a sufficiently low gate voltage to gate structure G.
As mentioned above, the configuration of conventional NFET 50 produces various parasitic capacitances that lead to poor isolation of NFET 50 in its off state. For descriptive purposes, these various parasitic capacitances are represented in FIG. 8(B) by capacitors C1 to C5, where parasitic capacitance C1 is a first vertical P-N junction capacitance formed by the interface between P-Well 55 and Deep N-Well 54, parasitic capacitance C2 is second a vertical P-N junction capacitance formed by the interface between Deep N-Well 54 and P-type substrate 51, parasitic capacitance C3 is a lateral (horizontal) P-N junction capacitance formed by the interface between P-Well 55 and N-Tap element 56, parasitic capacitance C4 is a peripheral overlap P-N junction capacitance generated between an overlap region 52O of third epi region 52-3 (i.e., part of N-Tap element 56) and P-type substrate 51 and created by an that typically occurs in conventional layouts, and parasitic capacitance C5 is a lateral (peripheral) P-N junction capacitance between N-Tap 56 and P-Tap 59. When utilized as a bulk CMOS RF switch, each of parasitic capacitances C1 to C5 contributes to generate a total parasitic capacitance to ground. This parasitic capacitance leads to poor isolation when NFET 50 is in an off state, causing undesirable leakage of an RF signal from the functional structures to ground. This reduces switch performance and increases battery consumption in mobile devices.
In a BiCMOS process the “native” silicon regions that are not implanted in any way (identified by regions 52R in FIG. 8(B)) are usually lightly doped n-type epitaxially grown silicon. In contrast, in a standard CMOS process the native silicon regions are typically part of the original silicon substrate, usually lightly-doped p-type.
What are needed are improved bulk CMOS RF switches that exhibit improved Ron-Coff characteristics over those exhibited by conventional bulk CMOS RF switch configurations. More specifically, what is needed is a cost-effective and reliable method for fabricating (manufacturing) bulk CMOS RF switches that achieve decreased Coff by way of reducing each switch's total parasitic capacitance without significantly increasing the switch's Ron, without significantly changing the switch's footprint (i.e., chip-area size), and without requiring expensive modifications to existing CMOS and BiCMOS fabrication flows.